Qualification：Bachelor or above degree

Recruiting Numbers：unlimited

Work Address：Chongqing/chengdu

Salary：

Update time：2025.08.20

1. Responsible for static timing analysis, including special timing confirmation, and collaborating with the front-end to optimize critical timing paths of modules, solve congestion problems, and meet input conditions for back-end physical implementation;
2. Based on the comprehensive results, guide the backend to implement area division, module layout, and solve congestion problems;
3. Assist DFT engineers in inserting and verifying DFT circuits;
4. Responsible for the comprehensive and formal verification of modules;
5. Participate in power consumption analysis of modules, work together with design and backend to complete power consumption optimization and area optimization of modules;
6. Participate in timing convergence iteration and sign off standards after backend layout and routing.

1. Bachelor's degree or above, major in electronics or computer related fields;
2. Proficient in chip synthesis, timing analysis, formal verification, familiar with DFT, and backend implementation;
3. Experience in physical implementation with advanced process nodes; Priority will be given to those with experience in chip fabrication at nodes of 28nm and below;
5. Experience in large-scale SOC physical implementation is preferred;
6. Proficient in using scripts such as Tcl, Perl, Python, etc. to establish automated processes;
7. Have good teamwork spirit and communication skills.

Qualification：Bachelor or above degree

Recruiting Numbers：unlimited

Work Address：Chongqing/chengdu

Salary：

Update time：2025.08.20

1. Responsible for or involved in the development of chip DFT testing plans;
2. Responsible for DFT implementation in MCU chips, including Scan, Mbist, ATPG, Boundary Scan, etc;
3. Complete the simulation verification of DFT test vectors;
4. Collaborate with the front-end and back-end teams for chip development, complete Timing/Power IR analysis and convergence related to the chip design process;
5. Assist the ATE testing team in failure analysis after generating test vectors and tape out, including vector debugging, coverage optimization, and solving problems encountered during testing;
6. Participate in the development and improvement of the digital DFT process.

1. Bachelor's degree or above in microelectronics, electronics, computer science or related fields, with at least 2 years of work experience;
2. Familiarity with Synopsy or Mentor DFT related EDA tools is preferred;
3. Master DFT circuit knowledge related to BSCAN, SCAN, MBISTL, BIST, and master timing analysis methods;
5. Have experience in ATPG and DFT simulation verification, and have the ability to independently analyze problems;
6. Familiar with scripting languages TCL/Python/Perl/Shell, with good scripting skills preferred;
7. Familiar with ASIC development process, with experience in 28nm and below process chip casting preferred;
8. Strong learning ability and problem-solving skills;
9. Good teamwork spirit, communication skills, and a serious and responsible work attitude.

Qualification：Bachelor or above degree

Recruiting Numbers：unlimited

Work Address：Chongqing/chengdu

Salary：

Update time：2025.08.20

1. Responsible for the physical design work of module RTL to GDS, including floorplan, powerplan, place, CTS, route;
2. Responsible for module timing convergence and signoff work, including timing analysis、signoff SI analysis、fix、formal、low power verification；
3. Responsible for the physical verification of modules, including DRC, ANT, LVS, IR, EM, ESD;
4. Participate in the development, improvement, evaluation, analysis, and validation of digital backend processes.

1. Bachelor's degree or above, major in electronics or computer related fields;
2. Proficient in the backend physical design process of chips from RTL to GDSII, proficient in using mainstream EDA tools;
3. Has extensive experience in Floorplan, P&R, STA, Physical Verification, and other areas;
4. Experience in physical implementation with advanced process nodes; Priority will be given to those with experience in chip fabrication at nodes of 28nm and below;
5. Experience in large-scale SOC physical implementation is preferred;
6. Proficient in using scripts such as Tcl, Perl, Python, etc. to establish automated processes;
7. Have good teamwork spirit and communication skills.