1. Responsible for simulating IC circuit schemes and architecture design;
2. Responsible for organizing and coordinating the internal work of the simulation team;
3. Responsible for developing specifications and conducting feasibility analysis for analog IC circuit modules, as well as designing and simulating specific circuits, and writing documents;
4. Assist layout design engineers in completing simulated IC layout design;
5. Responsible for post layout simulation and layout optimization;
6. Responsible for (or assisting testing engineers) developing testing plans and completing tests, as well as writing product testing specifications.
1. Experience in PLL, SDADC, or BUCK design is preferred;
2. Master's degree or above in microelectronics or related electronic information science;
3. Familiar with the design of Op amp, Band tap reference, OSC, and I/O modules;
4. Solid knowledge of circuit theory and IC design theory, familiar with CMOS technology;
5. CET-4 or above, with good English reading and writing skills;
6. Strong sense of responsibility, excellent communication skills, and a sense of teamwork.