• Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    Responsible for hardware work related to onboard chips, including:

    1. Responsible for the development of FPGA boards and chip verification boards for automotive chips;

    2. Responsible for the end-to-end hardware capability building and implementation of in vehicle chip solutions.


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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    Responsible for the driver development and verification of automotive MCU chip products, including:

    1. Provide MCAL software that complies with Autosar specifications for the delivery of chip products;

    2. Responsible for the underlying bridge of MCU chips, responsible for the implementation, verification, and hardware board debugging of underlying software modules related to ARM-M/R and RISC-V cores;

    3. Responsible for the development and validation of basic bus controller drivers for automotive MCU chip products, including but not limited to ETH, I2C, SPI, UART, CAN, LIN, etc.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    1. Participate in the development of analog IC specifications, responsible for circuit design and simulation verification, and write circuit design documents;

    2. Responsible for route optimization;

    3. Assist layout design engineers in completing simulated IC layout design;

    4. Write product testing specifications and assist testing engineers in developing testing plans.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    1. Responsible for layout design and verification of analog circuits, such as DRC/ANT/ERC/LVS, etc;

    2. Understand and analyze the process flow and design rules provided by the OEM, and comprehend the planar and hierarchical structures of the process components used;

    3. Communicate fully with design engineers to ensure a complete understanding of the design's requirements for the layout;

    4. Writing relevant documents;

    5. Assist design engineers in completing other related tasks.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    1. Responsible for the entire process of SOC/ASIC chips from netlist to tap out;

    2. Negotiate with front-end designers to solve problems encountered during the physical design process and optimize design solutions;

    3. Timely write various design documents and standardized materials to achieve resource and experience sharing.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    Responsible for ASIC chip design delivery and providing relevant process/engineering technical support, responsible for the quality, progress, and cost of delivered products.

    1. Responsible for the detailed physical design and verification of ASIC chips from RTL to GDSII, including physical architecture planning, layout and routing, power planning, clock tree synthesis, timing convergence, physical verification, power network analysis, and low-power design. Provide competitive solutions in PPA (performance, power consumption, cost) achievement, design, and process window matching;

    2. Responsible for ASIC chip DFT design and validation, accountable for testing costs, testing coverage, failure rates, and delivery times, providing competitive testing vectors and solutions, carrying out testing diagnostics, assisting in rapid process and testing problem localization.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.08.20

    1. Complete the analysis, design, and implementation of modules according to procedures and standards;

    2. Complete module documentation writing and maintenance according to document quality requirements, including logic design specifications, detailed design specifications, code inspection reports, user manuals, etc;

    3. Able to communicate and coordinate with verification personnel to solve problems encountered in module design, while also being able to perform simple module verification;

    4. Develop the subsystem project plan.

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  • Qualification:Bachelor or above degree
    Work Address:Chongqing/Chengdu
    Salary:
    Update time:2025.03.28

    1. Complete chip IP level, subsystem or system level functional verification and debugging work according to procedures and specifications;

    2. Participate in the decomposition of IP or system level verification function points and the development of verification plans for the assigned responsibilities;

    3. Participate in the construction of simulation and verification environments for the responsible IP or system level;

    4. Develop test vectors using UVM and conduct regression testing;

    5. Participate in planning and implementing various coverage analysis;

    6. Write and maintain validation documents for organizational subsystems, including validation plans, validation environment manuals, validation reports, etc;

    7. Communicate closely with the design team and coordinate the progress of verification work.


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headquarters address:4-5F, Building 10, Jintai Intelligent Industrial Park, Yubei District, Chongqing

Chengdu Branch:No. 1101, Building 2, Taihe International Financial Center, No. 619 Tianfu Third Street, Wuhou District, Chengdu City, Sichuan Province

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