- Qualification:Bachelor or above degree
- Recruiting Numbers:unlimited
- Work Address:Chongqing/Chengdu
- Salary:
- Update time:2025.08.20
Responsible for ASIC chip design delivery and providing relevant process/engineering technical support, responsible for the quality, progress, and cost of delivered products.
1. Responsible for the detailed physical design and verification of ASIC chips from RTL to GDSII, including physical architecture planning, layout and routing, power planning, clock tree synthesis, timing convergence, physical verification, power network analysis, and low-power design. Provide competitive solutions in PPA (performance, power consumption, cost) achievement, design, and process window matching;
2. Responsible for ASIC chip DFT design and validation, accountable for testing costs, testing coverage, failure rates, and delivery times, providing competitive testing vectors and solutions, carrying out testing diagnostics, assisting in rapid process and testing problem localization.
1. Bachelor's degree or above in microelectronics, computer science, communication engineering, automation and related majors.
2. Priority will be given to those who meet any of the following conditions:
(1) Proficient in deep sub micron backend physical design process, familiar with digital chip physical design tools such as Synopsys/Cadence, physical verification tools such as Calibre, and timing verification tools such as PT;
(2) Familiar with digital chip DFT or front-end logic design processes, familiar with digital circuit hardware description design languages such as Verilog, and knowledgeable or able to use Synopsys or Mentor related tools;
(3) The research direction is related to advanced semiconductor process technology and integrated development.
3. Passionate about work, responsible, meticulous in work, and strong in learning ability.
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