Campus Recruitment
- ASIC Design Engineer
Major oriented: microelectronics, integrated circuit, mathematics, physics, mechanics, materials, computer science and technology, communication engineering, chemistry, optical engineering, mechanical engineering, electromagnetic field and microwave technology, radio frequency antenna, instrumentation and other related majors
Work address: Chongqing/Chengdu
Job description:
1. Complete the analysis, design and implementation of modules according to the process and specification
2. Complete the document preparation and maintenance of the module according to the document quality requirements, including logic design instructions, detailed design instructions, code inspection reports, user manuals, etc
3. Be able to communicate and coordinate with the verifier to solve the problems encountered in the module design, and at the same time, be able to simply verify the module
4. Complete the formulation of subsystem project plan
Job requirements:
1. Bachelor degree or above in microelectronics, computer, communication engineering, automation, electromagnetic field, etc;
2. Have good communication and learning ability, and have a good sense of teamwork
3. Any one of the following conditions is preferred:
1) Have solid basic knowledge of digital circuit design, low-power design, performance optimization, etc
2) Familiar with verilog and other digital circuit hardware description design languages
3). Be familiar with the basic knowledge of computer architecture, understand the use of Linux, shell script programming, and master a script language, such as python, tcl, perl, etc
- ASIC Verification Engineer
Major oriented: microelectronics, integrated circuit, mathematics, physics, mechanics, materials, computer science and technology, communication engineering, chemistry, optical engineering, mechanical engineering, electromagnetic field and microwave technology, radio frequency antenna, instrumentation and other related majors
Work address: Chongqing/Chengdu
Job description:
1. Complete the verification and debugging of chip IP level, subsystem or system level functions according to the process and specification;
2. Participate in IP or system level verification function point decomposition and verification plan formulation;
3. Participate in the construction of the IP or system level simulation verification environment;
4. Use UVM to develop test vectors and conduct regression testing;
5. Participate in the planning and implementation of various coverage analysis.
6. Organize the compilation and maintenance of validation documents of subsystems, including validation plan, validation environment specification, validation report, etc
7. Closely communicate with the design team and coordinate the verification work
Job requirements:
1. Bachelor degree or above in microelectronics, electronic information, automation and other related majors;
2. Have good digital circuit and digital circuit foundation;
3、. Familiar with computer architecture, ARM architecture, system Verilog, UVM and formal verification methods. Relevant experience is preferred;
4. Good presentation and communication skills and teamwork ability.
- Digital back-end engineer
Major oriented: microelectronics, integrated circuit, mathematics, physics, mechanics, materials, computer science and technology, communication engineering, chemistry, optical engineering, mechanical engineering, electromagnetic field and microwave technology, radio frequency antenna, instrumentation and other related majors
Work address: Chongqing/Chengdu
Job description:
1. Responsible for the whole process of SOC chip/ASIC chip from netlist to tap out.
2. Negotiate with front-end designers to solve problems encountered in the physical design process and optimize the design scheme.
3. Timely prepare various design documents and standardized materials to share resources and experience.
DFT post:
Be responsible for the design and delivery of ASIC chips, provide relevant process/engineering technical support, and be responsible for the quality, progress and cost of the delivered products.
1. Be responsible for the detailed physical design and verification of ASIC chips from RTL to GDSII, including physical architecture planning, layout and routing, power planning, clock tree synthesis, timing convergence, physical verification, power network analysis and low power design, and provide competitive solutions in terms of PPA (performance, power consumption, cost) achievement, design/process window matching, etc;
2. Responsible for ASIC chip DFT design and verification, test cost, test coverage, failure rate and delivery time, providing competitive test vectors and solutions, carrying test diagnosis, assisting in rapid positioning of process and test problems.
Job requirements:
1. Familiar with the whole process of digital chip implementation (RTL to GDS);
2. Proficient in physical design, including floor plan, IO planning, power planning, placement, CTS, routing, timing fix, ECO, etc;
3. Proficient in physical verification, including DRC/LVS/ERC/Ant/DFM;
4. Proficient in more than one scripting language
5. He is enthusiastic about his work, has a sense of responsibility, works carefully, and has strong learning ability.
1. Bachelor degree or above in microelectronics, computer, communication engineering, mathematics, automation, materials, physics and other related majors;
2. Any one of the following conditions is preferred:
(1) Master the physical design process of deep submicron back-end, understand the digital chip physical design tools such as Synopsys/Cadence, physical verification tools such as Calibre, and timing verification tools such as PT;
(2) Familiar with digital chip DFT or front-end logic design process, familiar with verilog and other digital circuit hardware description design languages, understand or be able to use Synopsys or Mentor related tools;
(3) Research direction is related to advanced semiconductor process and integrated development
3. Full of enthusiasm for work, sense of responsibility, careful work and strong learning ability
- Digital IC Physical Implementation Engineer
Major oriented: microelectronics, integrated circuit, mathematics, physics, computer science and technology, communication engineering and other related majors
Work address: Chongqing/Chengdu
Job description:
1. Responsible for the development and script maintenance of EDA Flow implemented in the digital midrange of SOC chip
2. Responsible for clock scheme design, Floorplan design, low power consumption design (UPF), process and memory evaluation, Synthesis/STA/Formality and other tasks
3. Be responsible for the connection and communication between the front end and the rear end to reach the final PPA target
Job requirements:
1. Have the skills related to RTL to netlist delivery, including netlist synthesis, low power consumption check, static timing analysis, netlist form verification, etc., and be familiar with Synopsys or Cadence EDA tools;
2. Familiar with RTL design, able to fully communicate with front-end engineers and support RTL design optimization; Experience in clock reset design and low power design is preferred;
3. Familiar with the process and requirements of back-end PR, and STA signoff experience is preferred.
Resume delivery method:
Phone/WeChat：15730287339 / 13688069316
Mailbox：recruitment@lanshanae.com
